1. Field of the Invention
The present invention relates to a method of manufacturing a MOS transistor and more specifically a MOS transistor belonging to a memory point.
The present invention applies in particular to the manufacturing of memory points compatible with conventional CMOS transistor manufacturing methods.
2. Discussion of the Related Art
Floating gate memory points in which the control gate is formed of a layer diffused in a silicon substrate are known. Floating gate memory points with a single polysilicon level may thus be formed. An example of such a memory point is shown in FIG. 1. A MOS transistor T includes a drain region D and a source region S of type N.sup.+ formed in a P-type silicon substrate on either side of a gate G formed of a portion of a polysilicon region 10. Besides, polysilicon region 10 extends over a region 11 where it is arranged above an N.sup.+ -type region 12 formed in the substrate. Of course, when a P-type silicon substrate is mentioned, it may be a proper substrate, or an epitaxial layer on a silicon substrate, or a P-type well formed in a substrate. To simplify, the various connections have not been shown in FIG. 1. A drain terminal connected to region D, a source terminal connected to region S, and a control terminal connected to region 12 should clearly be provided. Such structures are well known in the art and will not be described in further detail hereafter. It should be understood that polysilicon region 10 forms a floating gate of transistor T, this floating gate being capacitively coupled with a control gate 12. The manufacturing method used will essentially be studied.
Conventionally, N.sup.+ -type region 12 is first formed in the P substrate, possibly at the same time as other regions of the integrated circuit in which the considered structure is formed. Then, after forming, in various locations silicon oxides of appropriate thicknesses, polysilicon region 10 is deposited and etched to form on the one hand region 11 capacitively coupled with control gate 12, and on the other hand, gate G of MOS transistor T. After this, the drain and source regions of the transistor are formed by using, in particular, the gate as a mask. Conventionally, these regions are formed in one or several steps with or without using spacers. It should be noted, especially for so-called flash memories, that the gate oxide under gate portion G is a tunnel oxide of small thickness and that the drain and source regions extend at least partially under the gate.
These various methods have been optimized essentially to promote the constitution of memory points, a great number of which are desired to be formed in a same chip. However, a disadvantage of these methods is to require a great number of manufacturing steps, especially when the source and drain regions are formed from several successive implantations.